Is the following Verilog code always synthesizable? I'm trying to use a variable as a bit select into a multibit variable:

`define MaxSize 5
wire[(`MaxSize-1):0] myVect;
wire                 myBit;
wire[3:0]            mySel;

// mySel can range from 0 to 15
assign myBit = (mySel < `MaxSize) ? myVect[mySel] : 0;

Next, I would like to extend to pulling out a range of bits:

`define MaxSize 5
wire[(`MaxSize*4)-1:0] myPackedArray;
wire[3:0]               myBits;
wire[3:0]               mySel;

// mySel can range from 0 to 15
assign myBits = (mySel < `MaxSize) ? myPackedArray[(mySel*4)+:4] : 0;

Do you see what I am trying to do? I don't want to overflow the bitselect for large mySel. It seemed to work in ModelSim, but I am interested in guaranteeing it will work in the final ASIC. I don't have access to the synthesis tool (Synopsys i think).

I am fine if the tool kicks it out as illegal, but my biggest fear is that it accepts it but does it wrong.
Gate-level simulation of the final ASIC functionality is not feasible. I had a silly case statement, but it needs adjusting every time MaxSize changes.

... should be ok, the bitslice is a constant width ... but need to be sure

Is the following Verilog code always synthesizable? I'm trying to use a variable as a bit select into a multibit variable:

`define MaxSize 5
wire[(`MaxSize-1):0] myVect;
wire                 myBit;
wire[3:0]            mySel;

// mySel can range from 0 to 15
assign myBit = (mySel < `MaxSize) ? myVect[mySel] : 0;

Next, I would like to extend to pulling out a range of bits:

`define MaxSize 5
wire[(`MaxSize*4)-1:0] myPackedArray;
wire[3:0]               myBits;
wire[3:0]               mySel;

// mySel can range from 0 to 15
assign myBits = (mySel < `MaxSize) ? myPackedArray[(mySel*4)+:4] : 0;

Do you see what I am trying to do? I don't want to overflow the bitselect for large mySel. It seemed to work in ModelSim, but I am interested in guaranteeing it will work in the final ASIC. I don't have access to the synthesis tool (Synopsys i think).

I am fine if the tool kicks it out as illegal, but my biggest fear is that it accepts it but does it wrong.
Gate-level simulation of the final ASIC functionality is not feasible. I had a silly case statement, but it needs adjusting every time MaxSize changes.

... should be ok, the bitslice is a constant width ... but need to be sure

• verilog
• system-verilog
• synthesis

• "Will it work in the final ASIC" is a more complex question than it being "synthesizable",. Would need to know what your timing, area, and power constraints are. – dave_59 Commented Feb 5 at 19:44

2 Answers 2

Your Verilog code looks synthesizable, but there is no guarantee that your Verilog code will synthesize the desired design on all synthesis tools. You need a method for determining if the synthesized design is correct. Asking people on the internet is not a substitute for your own verification method.

Here are some potential general issues:

• Different synthesis tools may support different Verilog syntax (even different versions of the same tool)
• The synthesis output you get could depend on your experience level with the tool (how you set the constraints, etc.)
• Synthesis tools have bugs, just like all software

Here are some methods of verification:

• Carefully read all synthesis output reports, looking for errors and warnings. Also look for informational messages which confirm your desired design.
• Run Verilog simulations on the output gate-level netlist. I'm not sure why you say this is not feasible. Companies do this every day. You run a huge risk by omitting this critical verification step.

I haven't tried it, but I'd be very surprised if this didn't work in DC. Have a look here for example Verilog and VHDL code which uses a variable mux select. This is a little dated, and is only tested on Xilinx XST, but synthesises identically (produces the same gate-level representation) as the equivalent conditional/case/if-else/etc 'static' code.

If your employer can afford DC, then they will very likely also be using an equivalence checker to confirm that the RTL is equivalent to the synthesised gates, which will handle the "does it wrong" problem.