What is a good way to test the interaction between two (or more) modules using cocotb?

For example, say we have a transmitter (TX) and receiver (RX) module, and we want to test them together (e.g., RX successfully synchronizes to TX).

// stream data to a receiver
module TX (
      input clk_i, rst_i,
      output data_o
      );

and

// receive data from a transmitter and synchronize to the data stream
module RX (
      input clk_i, rst_i, data_i,
      output sync_o
      );

I know how to test this using a Verilog testbench that instantiates and connects TX and RX. But how could one do this in cocotb? Would you first create a higher level module, TX_RX_tb.v, that instantiates TX and RX, and then becomes your DUT? Is there a way to connect the two modules in your cocotb python script instead of creating TX_RX_tb.v ?

module TX_RX_tb(
      input clk_i, rst_i,
      output sync_o
      );

wire data;

TX TX_inst(.clk_i(clk_i), .rst_i(rst_i), .data_o(data));
RX RX_inst(.clk_i(clk_i), .rst_i(rst_i), .data_i(data), .sync_o(sync_o));

What is a good way to test the interaction between two (or more) modules using cocotb?

For example, say we have a transmitter (TX) and receiver (RX) module, and we want to test them together (e.g., RX successfully synchronizes to TX).

// stream data to a receiver
module TX (
      input clk_i, rst_i,
      output data_o
      );

and

// receive data from a transmitter and synchronize to the data stream
module RX (
      input clk_i, rst_i, data_i,
      output sync_o
      );

I know how to test this using a Verilog testbench that instantiates and connects TX and RX. But how could one do this in cocotb? Would you first create a higher level module, TX_RX_tb.v, that instantiates TX and RX, and then becomes your DUT? Is there a way to connect the two modules in your cocotb python script instead of creating TX_RX_tb.v ?

module TX_RX_tb(
      input clk_i, rst_i,
      output sync_o
      );

wire data;

TX TX_inst(.clk_i(clk_i), .rst_i(rst_i), .data_o(data));
RX RX_inst(.clk_i(clk_i), .rst_i(rst_i), .data_i(data), .sync_o(sync_o));

• python
• verilog
• system-verilog
• hdl
• cocotb

1 Answer 1

From the cocotb github discussion page, the recommended answer is to use a simple module that wires together the DUTs you want to test.

https://github/cocotb/cocotb/issues/385

I recommend you to use a "harness" Verilog module. In this module you can instantiate DUTs in various configuration. From the Cocotb perspective your simulated top level will be the harness, instead of a standalone DUT.