I am making a mockup CPU in VHDL. I am using Vivado for simulation and programming environment. I need help understanding why my simulation won't follow through with the nestled loops.
I need opcode_tb to go through 0-15 to make sure every opcode works yet when I simulate it only goes up to 2. The ax_tb goes through 0-15 while the opcode goes up to 2. I have tried having more time for the loop to update yet it doesn't change anything.
Is it possible to update the loops while they are running?
Is this a problem with Vivado? Or with the code/coder self? Should I find another solution for looping through 0-15?
The opcode of course doesn't need to be in a row, and I had thoughts that maybe doing a random number generator would work better.
Test bench:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_cpu is
end tb_cpu;
architecture Behavioral of tb_cpu is
component cpu
Port (
clk : in STD_LOGIC;
update : in STD_LOGIC;
ax : in STD_LOGIC_VECTOR(3 downto 0);
opcode : in STD_LOGIC_VECTOR(3 downto 0);
A : out STD_LOGIC_VECTOR(3 downto 0);
B : out STD_LOGIC_VECTOR(3 downto 0);
C : out STD_LOGIC_VECTOR(3 downto 0);
D : out STD_LOGIC_VECTOR(3 downto 0)
);
end component;
signal clk_tb : STD_LOGIC := '0';
signal update_tb : STD_LOGIC := '0';
signal ax_tb : STD_LOGIC_VECTOR(3 downto 0);
signal opcode_tb : STD_LOGIC_VECTOR(3 downto 0);
signal A_tb : STD_LOGIC_VECTOR(3 downto 0);
signal B_tb : STD_LOGIC_VECTOR(3 downto 0);
signal C_tb : STD_LOGIC_VECTOR(3 downto 0);
signal D_tb : STD_LOGIC_VECTOR(3 downto 0);
constant clk_period : time := 10 ns;
begin
uut : cpu
Port map (
clk => clk_tb,
update => update_tb,
ax => ax_tb,
opcode => opcode_tb,
A => A_tb,
B => B_tb,
C => C_tb,
D => D_tb
);
clk_process : process
begin
clk_tb <= '0';
wait for clk_period / 2;
clk_tb <= '1';
wait for clk_period / 2;
end process;
stim_proc : process
begin
update_tb <= '0';
ax_tb <= (others => '0');
opcode_tb <= (others => '0');
wait for clk_period * 5;
update_tb <= '1';
for j in 0 to 15 loop
for i in 0 to 15 loop
ax_tb <= std_logic_vector(to_signed(i, 4));
opcode_tb <= std_logic_vector(to_signed(j, 4));
wait for clk_period * 2;
end loop;
end loop;
wait;
end process;
end Behavioral;
CPU code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_std.all;
entity cpu is
Port (
clk : in STD_LOGIC;
update : in STD_LOGIC;
ax : in STD_LOGIC_VECTOR(3 downto 0);
opcode : in STD_LOGIC_VECTOR(3 downto 0);
A : out STD_LOGIC_VECTOR(3 downto 0);
B : out STD_LOGIC_VECTOR(3 downto 0);
C : out STD_LOGIC_VECTOR(3 downto 0);
D : out STD_LOGIC_VECTOR(3 downto 0) );
end cpu;
architecture Behaving of cpu is
component cu
Port (
clk : in STD_LOGIC;
update : in STD_LOGIC;
ax : in STD_LOGIC_VECTOR(3 downto 0);
opcode : in STD_LOGIC_VECTOR(3 downto 0);
result_add : inout STD_LOGIC_VECTOR(4 downto 0);
result_mult : inout STD_LOGIC_VECTOR(7 downto 0);
result_not : inout STD_LOGIC_VECTOR(3 downto 0);
result_and : inout STD_LOGIC_VECTOR(3 downto 0);
result_or : inout STD_LOGIC_VECTOR(3 downto 0);
BX : inout STD_LOGIC_VECTOR(3 downto 0);
CX : out STD_LOGIC_VECTOR(3 downto 0);
DX : out STD_LOGIC_VECTOR(3 downto 0);
op_in1 : out STD_LOGIC_VECTOR(3 downto 0);
op_in2 : out STD_LOGIC_VECTOR(3 downto 0)
);
end component;
signal temp_bx, temp_cx, temp_dx : STD_LOGIC_VECTOR(3 downto 0);
signal alu_in1, alu_in2 : STD_LOGIC_VECTOR(3 downto 0);
signal result_add : STD_LOGIC_VECTOR(4 downto 0);
signal result_mult : STD_LOGIC_VECTOR(7 downto 0);
signal result_not, result_and, result_or : STD_LOGIC_VECTOR(3 downto 0);
begin
cu_inst : cu
port map (
clk => clk,
update => update,
ax => ax,
opcode => opcode,
result_add => result_add,
result_mult => result_mult,
result_not => result_not,
result_and => result_and,
result_or => result_or,
BX => temp_bx,
CX => temp_cx,
DX => temp_dx,
op_in1 => alu_in1,
op_in2 => alu_in2
);
A <= temp_bx;
B <= temp_cx;
C <= temp_cx;
D <= temp_dx;
end Behaving;
library IEEE;
use IEEE.std_logic_1164.all;
entity cu is
Port (
clk : in STD_LOGIC;
update : in STD_LOGIC;
ax : in STD_LOGIC_VECTOR(3 downto 0);
opcode : in STD_LOGIC_VECTOR(3 downto 0);
result_add : inout STD_LOGIC_VECTOR(4 downto 0);
result_mult : inout STD_LOGIC_VECTOR(7 downto 0);
result_not : inout STD_LOGIC_VECTOR(3 downto 0);
result_and : inout STD_LOGIC_VECTOR(3 downto 0);
result_or : inout STD_LOGIC_VECTOR(3 downto 0);
BX : inout STD_LOGIC_VECTOR(3 downto 0);
CX : out STD_LOGIC_VECTOR(3 downto 0);
DX : out STD_LOGIC_VECTOR(3 downto 0);
op_in1 : out STD_LOGIC_VECTOR(3 downto 0);
op_in2 : out STD_LOGIC_VECTOR(3 downto 0)
);
end cu;
architecture Behave of cu is
component alu
port (
in_1 : in STD_LOGIC_VECTOR(3 downto 0);
in_2 : in STD_LOGIC_VECTOR(3 downto 0);
out_add : inout STD_LOGIC_VECTOR(4 downto 0);
out_mult : inout STD_LOGIC_VECTOR(7 downto 0);
out_not : inout STD_LOGIC_VECTOR(3 downto 0);
out_and : inout STD_LOGIC_VECTOR(3 downto 0);
out_or : inout STD_LOGIC_VECTOR(3 downto 0)
);
end component;
signal alu_in1, alu_in2 : STD_LOGIC_VECTOR(3 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if update = '1' then
case opcode is
when "0000" =>
BX <= ax;
when "0001" =>
CX <= ax;
when "0010" =>
DX <= ax;
when "0011" =>
BX <= "1111";
when "0100" =>
CX <= "1111";
when "0101" =>
DX <= "1111";
when "0110" =>
alu_in1 <= "0010";
alu_in2 <= "0011";
CX <= result_add(3 downto 0);
DX <= "0101";
when "0111" =>
alu_in1 <= "0010";
alu_in2 <= "0011";
CX <= result_mult(3 downto 0);
DX <= "0110";
when "1000" =>
alu_in1 <= "0010";
CX <= result_not;
DX <= "1101";
when "1001" =>
alu_in1 <= "0010";
alu_in2 <= "0011";
CX <= result_and;
DX <= "0010";
when "1010" =>
alu_in1 <= "0010";
alu_in2 <= "0011";
CX <= result_or;
DX <= "0011";
when "1011" =>
alu_in1 <= ax;
alu_in2 <= BX;
DX <= (result_add(3 downto 0) and "000");
CX <= result_add(3 downto 0);
when "1100" =>
alu_in1 <= ax;
alu_in2 <= BX;
DX <= result_mult(7 downto 4);
CX <= result_mult(3 downto 0);
when "1101" =>
alu_in1 <= ax;
CX <= result_not;
DX <= "0000";
when "1110" =>
alu_in1 <= ax;
alu_in2 <= BX;
CX <= result_and;
DX <= "0000";
when "1111" =>
alu_in1 <= ax;
alu_in2 <= BX;
CX <= result_or;
DX <= "0000";
when others =>
BX <= (others => '0');
CX <= (others => '0');
DX <= (others => '0');
end case;
end if;
end if;
end process;
alu_inst : alu
port map (
in_1 => alu_in1,
in_2 => alu_in2,
out_add => result_add,
out_mult => result_mult,
out_not => result_not,
out_and => result_and,
out_or => result_or
);
end Behave;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_std.all;
entity alu is
Port (
in_1 : in STD_LOGIC_VECTOR(3 downto 0);
in_2 : in STD_LOGIC_VECTOR(3 downto 0);
out_add : inout STD_LOGIC_VECTOR(4 downto 0);
out_mult : inout STD_LOGIC_VECTOR(7 downto 0);
out_not : inout STD_LOGIC_VECTOR(3 downto 0);
out_and : inout STD_LOGIC_VECTOR(3 downto 0);
out_or : inout STD_LOGIC_VECTOR(3 downto 0));
end alu;
architecture Behavioral of alu is
component add4
port ( in_1 : in STD_LOGIC_VECTOR (3 downto 0);
in_2 : in STD_LOGIC_VECTOR (3 downto 0);
s_out : out STD_LOGIC_VECTOR (4 downto 0));
end component;
component mul4
port ( in_1 : in STD_LOGIC_VECTOR (3 downto 0);
in_2 : in STD_LOGIC_VECTOR (3 downto 0);
m_out : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component invrt4
port ( in_1 : in STD_LOGIC_VECTOR (3 downto 0);
i_out : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component bit_and4
port ( in_1 : in STD_LOGIC_VECTOR (3 downto 0);
in_2 : in STD_LOGIC_VECTOR (3 downto 0);
a_out : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component bit_or4
Port ( in_1 : in STD_LOGIC_VECTOR (3 downto 0);
in_2 : in STD_LOGIC_VECTOR (3 downto 0);
o_out : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal input1, input2 : STD_LOGIC_VECTOR(3 downto 0);
signal temp_add : STD_LOGIC_VECTOR(4 downto 0);
signal temp_mult : STD_LOGIC_VECTOR(7 downto 0);
signal temp_not : STD_LOGIC_VECTOR(3 downto 0);
signal temp_and : STD_LOGIC_VECTOR(3 downto 0);
signal temp_or : STD_LOGIC_VECTOR(3 downto 0);
begin
add1 : add4 port map (in_1 => in_1, in_2 => in_2, s_out => temp_add);
mul1 : mul4 port map (in_1 => in_1, in_2 => in_2, m_out => temp_mult);
not1 : invrt4 port map (in_1 => in_1, i_out => temp_not);
and1 : bit_and4 port map (in_1 => in_1, in_2 => in_2, a_out => temp_and);
or1 : bit_or4 port map (in_1 => in_1, in_2 => in_2, o_out => temp_or);
out_add <= temp_add;
out_mult <= temp_mult;
out_not <= temp_not;
out_and <= temp_and;
out_or <= temp_or;
end Behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity add4 is
Port ( in_1 : in STD_LOGIC_VECTOR (3 downto 0);
in_2 : in STD_LOGIC_VECTOR (3 downto 0);
s_out : out STD_LOGIC_VECTOR (4 downto 0));
end add4;
architecture Behavioral of add4 is
begin
process(in_1, in_2)
begin
s_out <= std_logic_vector(unsigned('0' & in_1) + unsigned('0' & in_2));
end process;
end Behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity mul4 is
Port ( in_1 : in STD_LOGIC_VECTOR (3 downto 0);
in_2 : in STD_LOGIC_VECTOR (3 downto 0);
m_out : out STD_LOGIC_VECTOR (7 downto 0));
end mul4;
architecture Behav of mul4 is
begin
process(in_1, in_2)
begin
m_out <= std_logic_vector(unsigned('0' & in_1) * unsigned('0' & in_2));
end process;
end Behav;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity invrt4 is
Port ( in_1 : in STD_LOGIC_VECTOR (3 downto 0);
i_out : out STD_LOGIC_VECTOR (3 downto 0));
end invrt4;
architecture Behavinvrt of invrt4 is
begin
process(in_1)
begin
i_out <= not(in_1);
end process;
end Behavinvrt;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity bit_and4 is
Port ( in_1 : in STD_LOGIC_VECTOR (3 downto 0);
in_2 : in STD_LOGIC_VECTOR (3 downto 0);
a_out : out STD_LOGIC_VECTOR (3 downto 0));
end bit_and4;
architecture behavand of bit_and4 is
begin
process(in_1, in_2)
begin
a_out <= in_1 and in_2;
end process;
end behavand;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity bit_or4 is
Port ( in_1 : in STD_LOGIC_VECTOR (3 downto 0);
in_2 : in STD_LOGIC_VECTOR (3 downto 0);
o_out : out STD_LOGIC_VECTOR (3 downto 0));
end bit_or4;
architecture behavor of bit_or4 is
begin
process(in_1, in_2)
begin
o_out <= ( in_1 OR in_2);
end process;
end behavor;
My simulation stops at 2 and proceeds no further. It halts and ends the simulation.