I would like to get an explanation or be directed to a specific literature to understand the behavior below. I am using Digilent NEXSYS-A7-100t with AMD Vivado. And running post-implementation timing simulation.

My vhdl code is here:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

entity sbs_counter is
    Port ( 
        CLK100MHZ : in std_logic;
        start : in std_logic;
        load : in std_logic;
        upper_limit : out std_logic;
        counter_out : out std_logic_vector(7 downto 0)
    );
end sbs_counter;

architecture Behavioral of sbs_counter is
    signal counter_in_int : std_logic_vector(7 downto 0);
    signal counter_out_int : std_logic_vector(7 downto 0) := x"00";
    signal upper_limit_int : std_logic;
begin
    counter_in_int <= x"04";
    counter_out <= counter_out_int;
    upper_limit <= upper_limit_int;
    process (CLK100MHZ) begin
        if rising_edge(CLK100MHZ) then
            if (load = '1') then
                 counter_out_int <= counter_in_int;
            elsif (start = '1') then
                counter_out_int <= counter_out_int + '1';
            end if;
        end if;
    end process;
    upper_limit_int <= counter_out_int(4);
end Behavioral;

my test-bench code is here:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sbs_counter_tb is
end sbs_counter_tb;

architecture Behavioral of sbs_counter_tb is
    component sbs_counter is
        Port ( 
            CLK100MHZ : in std_logic;
            start : in std_logic;
            load : in std_logic;
            upper_limit : out std_logic;
            counter_out : out std_logic_vector(7 downto 0)
        );
    end component;
    signal clk_int : std_logic;
    signal start_int : std_logic;
    signal load_int : std_logic;
    signal upper_limit_int : std_logic := '0';
    signal counter_out_int : std_logic_vector(7 downto 0);
begin
    DTU: sbs_counter port map (
        CLK100MHZ => clk_int,
        start => start_int,
        load => load_int,
        upper_limit => upper_limit_int,
        counter_out => counter_out_int
    );

    process
    begin
        clk_int <= '0';
        start_int <= '0';
        load_int <= '0';
        wait for 50 ns;
        
        clk_int <= '0';
        start_int <= '0';
        load_int <= '1';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '0';
        load_int <= '1';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '0';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;

        clk_int <= '1';
        start_int <= '1';
        load_int <= '0';
        wait for 50 ns;
        wait;
    end process;
end Behavioral;

This test-bench produces a normal behavior:

While when I reduce the clock cycle from 100ns to 10ns, the counter does not respond to clock signal for the first nine cycles and starts counting with the tenth cycle. You can see the counter didn't load the starting number and start counting at the tenth cycle. Why is that?

If I generate ten cycles before loading and start counting, the counter works directly Why the 10 cycles at the start of the test-bench is needed to get the counter loads and counts normally?