I'm trying to create a Makefile for compiling a Linux kernel module with multiple source files. However, I encounter a compilation error unless I manually specify the object files.

Header Files:

`Fun.h`

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>

int Fun(int Arg);

simple_lkm.h

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include "Fun.h"

#define MODULE_NAME "SimpleLKM"

int __init simple_lkm_init(void);
void __exit simple_lkm_exit(void);

Source Files:

`Fun.c`

#include "Fun.h"

int Fun(int Arg)
{
    return Arg + 777;
}

simple_lkm.c

#include "simple_lkm.h"

MODULE_LICENSE("Dual MIT/GPL");

module_init(simple_lkm_init);
module_exit(simple_lkm_exit);

//////////////////////////////////////////////////////////////
int __init simple_lkm_init(void)
{
    printk("%s: simple_lkm_init called\n", MODULE_NAME);
    int res = Fun(0);
    printk("res = %d\n", res);
    printk("%s: simple_lkm_init completed\n", MODULE_NAME);
    
    return 0;
}

//////////////////////////////////////////////////////////////
void __exit simple_lkm_exit(void)
{
    printk("%s: simple_lkm_exit called\n", MODULE_NAME);
    printk("%s: simple_lkm_exit completed\n", MODULE_NAME);
}

`Makefile`

MODULE_NAME := SimpleLKM2
PWD := $(shell pwd)
KERNEL := $(shell uname -r)


SRCS := $(wildcard *.c)
#OBJS := $(SRCS:.c=.o)
OBJS := simple_lkm.o Fun.o

obj-m := $(MODULE_NAME).o
$(MODULE_NAME)-y := $(OBJS)

all: 
    make -C /lib/modules/$(KERNEL)/build  M=$(PWD) modules
    
clean:
    make -C /lib/modules/$(KERNEL)/build M=$(PWD) clean
    

.PHONY: all clean

Compilation failed with the following message:

make -C /lib/modules/6.11.0-21-generic/build  M=/home/dev/LKM/SimpleLKM modules make[1]: Entering directory '/usr/src/linux-headers-6.11.0-21-generic' warning: the compiler differs from the one used to build the kernel The kernel was built by: x86_64-linux-gnu-gcc-13 (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0 You are using:           gcc-13 (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0 make[3]: *** No rule to make target '/home/dev/LKM/SimpleLKM/SimpleLKM2.o', needed by '/home/dev/LKM/SimpleLKM/'.  Stop. make[2]: *** [/usr/src/linux-headers-6.11.0-21-generic/Makefile:1932: /home/dev/LKM/SimpleLKM] Error 2 make[1]: *** [Makefile:224: __sub-make] Error 2 make[1]: Leaving directory '/usr/src/linux-headers-6.11.0-21-generic' make: *** [Makefile:15: all] Error 2

However, if I manually set OBJS := simple_lkm.o Fun.o, compilation succeeds.

How should I modify the Makefile so that it correctly automates object file generation without manually specifying OBJS?

I'm trying to create a Makefile for compiling a Linux kernel module with multiple source files. However, I encounter a compilation error unless I manually specify the object files.

Header Files:

`Fun.h`

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>

int Fun(int Arg);

simple_lkm.h

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include "Fun.h"

#define MODULE_NAME "SimpleLKM"

int __init simple_lkm_init(void);
void __exit simple_lkm_exit(void);

Source Files:

`Fun.c`

#include "Fun.h"

int Fun(int Arg)
{
    return Arg + 777;
}

simple_lkm.c

#include "simple_lkm.h"

MODULE_LICENSE("Dual MIT/GPL");

module_init(simple_lkm_init);
module_exit(simple_lkm_exit);

//////////////////////////////////////////////////////////////
int __init simple_lkm_init(void)
{
    printk("%s: simple_lkm_init called\n", MODULE_NAME);
    int res = Fun(0);
    printk("res = %d\n", res);
    printk("%s: simple_lkm_init completed\n", MODULE_NAME);
    
    return 0;
}

//////////////////////////////////////////////////////////////
void __exit simple_lkm_exit(void)
{
    printk("%s: simple_lkm_exit called\n", MODULE_NAME);
    printk("%s: simple_lkm_exit completed\n", MODULE_NAME);
}

`Makefile`

MODULE_NAME := SimpleLKM2
PWD := $(shell pwd)
KERNEL := $(shell uname -r)


SRCS := $(wildcard *.c)
#OBJS := $(SRCS:.c=.o)
OBJS := simple_lkm.o Fun.o

obj-m := $(MODULE_NAME).o
$(MODULE_NAME)-y := $(OBJS)

all: 
    make -C /lib/modules/$(KERNEL)/build  M=$(PWD) modules
    
clean:
    make -C /lib/modules/$(KERNEL)/build M=$(PWD) clean
    

.PHONY: all clean

Compilation failed with the following message:

make -C /lib/modules/6.11.0-21-generic/build  M=/home/dev/LKM/SimpleLKM modules make[1]: Entering directory '/usr/src/linux-headers-6.11.0-21-generic' warning: the compiler differs from the one used to build the kernel The kernel was built by: x86_64-linux-gnu-gcc-13 (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0 You are using:           gcc-13 (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0 make[3]: *** No rule to make target '/home/dev/LKM/SimpleLKM/SimpleLKM2.o', needed by '/home/dev/LKM/SimpleLKM/'.  Stop. make[2]: *** [/usr/src/linux-headers-6.11.0-21-generic/Makefile:1932: /home/dev/LKM/SimpleLKM] Error 2 make[1]: *** [Makefile:224: __sub-make] Error 2 make[1]: Leaving directory '/usr/src/linux-headers-6.11.0-21-generic' make: *** [Makefile:15: all] Error 2

However, if I manually set OBJS := simple_lkm.o Fun.o, compilation succeeds.

How should I modify the Makefile so that it correctly automates object file generation without manually specifying OBJS?

• linux
• makefile
• kernel

• Please be sure to preview / review your question and make sure the formatting is correct, when posting. Thanks! – MadScientist Commented Apr 1 at 12:52
• This question is similar to: Cannot use wildcard in kernel module makefile. If you believe it’s different, please edit the question, make it clear how it’s different and/or how the answers on that question are not helpful for your problem. – Tsyvarev Commented yesterday

1 Answer 1

You cannot use wildcard like this with kernel makefiles. The way kernel makefiles work is they run a sub-make in a separate directory, and when that sub-make runs the $(wildcard ...) function will not match any files, because the current working directory is not the one containing your makefile (and sources).

See the command:

    make -C /lib/modules/$(KERNEL)/build  M=$(PWD) modules

The -C option tells make to switch to a different directory and run make there instead.

You have to explicitly list your files, as you've done here.