Any variable that is declared inside a task or function without specifying type will be considered automatic. To specify that a variable is static place the "static" keyword in the declaration before the type, e.g., "static int x;". The "automatic" keyword is used in the same way.

This is what I found on Wikipedia article.

But, I'm getting an error in below scenario.

module MouduleName ();
function int getNumberDivisableValue(int divisibleNumber);
     int number_divisable_value = 0;  // Not explicitly declared as automatic
     // automatic int number_divisable_value = 0;  // working as expected if it's explicitly declared as automatic
    while (!number_divisable_value) begin
      number_divisable_value = $urandom_range(URANDOM_MIN_RANGE, URANDOM_MAX_RANGE);
      if (number_divisable_value % divisibleNumber == 0) begin
        return number_divisable_value;
      end else begin
        number_divisable_value = 0;
      end
    end
  endfunction

 initial begin
    //function call
 end

endmodule

Error (suppressible): array_manipulation.sv(18): (qverilog-2244) Variable 'number_divisable_value' is implicitly static. You must either explicitly declare it as static or automatic or remove the initialization in the declaration of variable.

But, if the variable is declared explicitly as automatic, I'm not getting above error. If the variable inside a function or task is automatic by default, then why I am getting an error and why not if it is explicitly declared as automatic?

If we can't initialize an automatic variable while declaring in SystemVerilog, but how can we do in programming language like Java or other software languages (dynamic variable)?

Tool : I've been using QuestaSim

Any variable that is declared inside a task or function without specifying type will be considered automatic. To specify that a variable is static place the "static" keyword in the declaration before the type, e.g., "static int x;". The "automatic" keyword is used in the same way.

https://en.wikipedia./wiki/SystemVerilog

This is what I found on Wikipedia article.

But, I'm getting an error in below scenario.

module MouduleName ();
function int getNumberDivisableValue(int divisibleNumber);
     int number_divisable_value = 0;  // Not explicitly declared as automatic
     // automatic int number_divisable_value = 0;  // working as expected if it's explicitly declared as automatic
    while (!number_divisable_value) begin
      number_divisable_value = $urandom_range(URANDOM_MIN_RANGE, URANDOM_MAX_RANGE);
      if (number_divisable_value % divisibleNumber == 0) begin
        return number_divisable_value;
      end else begin
        number_divisable_value = 0;
      end
    end
  endfunction

 initial begin
    //function call
 end

endmodule

Error (suppressible): array_manipulation.sv(18): (qverilog-2244) Variable 'number_divisable_value' is implicitly static. You must either explicitly declare it as static or automatic or remove the initialization in the declaration of variable.

But, if the variable is declared explicitly as automatic, I'm not getting above error. If the variable inside a function or task is automatic by default, then why I am getting an error and why not if it is explicitly declared as automatic?

If we can't initialize an automatic variable while declaring in SystemVerilog, but how can we do in programming language like Java or other software languages (dynamic variable)?

Tool : I've been using QuestaSim

• function
• task
• verilog
• system-verilog
• questasim

2 Answers 2

The information in the Wikipedia article is incomplete. You need to refer to the IEEE Std 1800-2023 for more details. It distinguishes between functions with implicit or explicit lifetimes, based on whether the function is declared inside a module or class, for example.

Based on that, you can then determine the rules for variables within the function.

The error message explains the reason the simulator considers it an error. Refer to the QuestaSim documentation to see if there is further information on the "qverilog-2244" category. The error is also labeled "suppressible", which I presume means you can suppress the error by configuring your tool differently. I don't have experience with QuestaSim, so, again, read the documentation. Before suppressing the error, you should fully understand the implications of doing so.

Other simulators allow this in varying degrees. For example, I placed your function inside a module, and the Cadence simulator generated a warning message similar to the QuestaSim error message you got. It was only a warning (not an error), which means the simulation could run.

By default, the Synopsys simulator did not generate any message. I needed to explicitly enable linting to see the similar warning message to the other 2 simulators. Try your code on EDA Playground to see what I mean.

The Wikipedia article is not correct. The implicit lifetime of variable declared inside a task for function matches the lifetime of of the task or function.

Assuming your function is not declared as a class method, its default lifetime is static, which makes the variable lifetime static. Almost all other languages have functions with automatic lifetimes and have no concept of functions with static lifetimes. That's reason why that code is illegal and is further explained here.

There are a number of way to change the lifetime of a function discussed in the LRM so you do not run into this issue.