I am assigning a wire with logic between a register and a counter.

wire wire1;
reg  signal;
reg [5:0] count;

assign wire1 = signal & !|count;   // line 1
assign wire1 = signal & ! |count;  // line 2
assign wire1 = signal & !(|count); // line 3
assign wire1 = signal & ~|count;   // line 4

Icarus gives an error for 'line 1' and 'line 2', but not 'line 3' and 'line 4'. The message is,

Operand of unary ! is not a primary expression

I think it is a parser error (both work with brackets). I am using |count as count==0 but found the reduction easier as many tools will complain about bit length of text '0' as 32 bits. I.e., I need count==COUNT_ZERO where it is some local parameter of the correct length.

Is there actually a difference between '!' and '~' for one-bit constructs?

I am assigning a wire with logic between a register and a counter.

wire wire1;
reg  signal;
reg [5:0] count;

assign wire1 = signal & !|count;   // line 1
assign wire1 = signal & ! |count;  // line 2
assign wire1 = signal & !(|count); // line 3
assign wire1 = signal & ~|count;   // line 4

Icarus gives an error for 'line 1' and 'line 2', but not 'line 3' and 'line 4'. The message is,

Operand of unary ! is not a primary expression

I think it is a parser error (both work with brackets). I am using |count as count==0 but found the reduction easier as many tools will complain about bit length of text '0' as 32 bits. I.e., I need count==COUNT_ZERO where it is some local parameter of the correct length.

Is there actually a difference between '!' and '~' for one-bit constructs?

• verilog
• system-verilog

• Well, I know the answer after looking at precedence table, but this is a little bit of a surprise as other languages do not use multi-character operators. – artless-noise-bye-due2AI Commented Jan 31 at 17:03
• @toolic the '~|' is a nor reduction where as '!|' is syntactically different. I can delete this question, if you think that is obvious. It is not as most languages with a 'C' heritage do not behave like this, so it is a verilog specific issue. Of course reductions are already different... but it was surprising to me. – artless-noise-bye-due2AI Commented Jan 31 at 17:05
• Also, it is wrong to say other languages don't use multi-characters. Some example, i++, a || b, a && b, p->elem, etc. It is not 'precedence' in a traditional sense and white space may matter, so it is a lexical issue. Of course, '!' and '~' by themselves are equivalent, my misconceptions was that they were individual tokens. – artless-noise-bye-due2AI Commented Feb 4 at 13:55

2 Answers 2

As you mentioned in the comments on your question, this is the difference between your 2 lines:

• ~|: These 2 characters form a single operator, namely the reduction-OR
• !|: These 2 characters represent two operators, namely logic-NOT and bitwise OR

Almost all simulators on EDA Playground generate a compile error on this line:

assign wire1 = signal & !|count;  // line 1

This means the problem is not limited to the Icarus Verilog (iverilog) simulator.

From a coding style perspective, I prefer creating a new wire just for this expression:

wire counter_expired = |count;

Verilog/SystemVerilog has multi character operands and has BNF rules to prevent misunderstandings like this. In this case it has nothing to do with the width of the operands. Use parentheses or a space to separate the operators.