心得体会.
如下是一个简单地分频在quartus中与modelsim中相同的VHDL代码却在quartus中得到正确结果，而modelsim中却不可以得到。花了半天时间终于找到原因（在modelsim中默认为高阻,而quartus中默认为0电平，一定注意在modelsim中仿真的信号量的反转一定要给一个初始值）；希望和我一样的菜鸟能够少走弯路，在modelsim中仿真时注意信号的赋初始值，特别是有电平翻转的信号。例子如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Exp2_38decoder IS
PORT( clk : IN STD_LOGIC;
clk_div_4 : OUT STD_LOGIC);
END Exp2_38decoder;
ARCHITECTURE one OF Exp2_38decoder IS
CONSTANT m:INTEGER:=2; --four divide coefficient
SIGNAL clk_r: STD_LOGIC;
BEGIN
PROCESS(clk)
VARIABLE cnt1: INTEGER RANGE 0 TO m-1;
BEGIN
IF RISING_EDGE(clk) THEN
IF cnt1<m-1 THEN
cnt1:=cnt1+1;
ELSE
cnt1:=0;
clk_r <= NOT clk_r; --get the wave of D=50%
END IF;
END IF;
clk_div_4<=clk_r;
END PROCESS;
END one;
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MODELSIM
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY div_fre_4 IS
PORT( clk : IN STD_LOGIC;
clk_div_4 : OUT STD_LOGIC);
END div_fre_4;
ARCHITECTURE one OF div_fre_4 IS
CONSTANT m:INTEGER:=2; --four divide coefficient
SIGNAL clk_r: STD_LOGIC := '0'; --加上这句才能够在modelsim中仿真成功,这个几乎半天时间才找到原因;(在modelsim中默认为高阻,而quartus中默认为0电平，一定注意在modelsim中仿真的信号量的反转一定要给一个初始值)
BEGIN
PROCESS(clk)
VARIABLE cnt1: INTEGER RANGE 0 TO m-1;
BEGIN
IF (clk'event AND clk = '1') THEN
IF cnt1<m-1 THEN
cnt1:=cnt1+1;
ELSE
cnt1:=0;
clk_r <= NOT clk_r; --get the wave of D=50%
END IF;
END IF;
clk_div_4<=clk_r;
END PROCESS;
END one;