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2N7008

N-Channel Enhancement-Mode

Vertical DMOS FETs

Ordering Information

BV/ RI

DSSDS(ON)D(ON)

BV(max)(min)TO-92

DGS

60V7.5Ω500mA2N7008

Order Number / Package

FeaturesAdvanced DMOS Technology

Free from secondary breakdown

Low power drive requirement

Ease of paralleling

Low C

ISS

and fast switching speeds

Excellent thermal stability

Integral Source-Drain diode

High input impedance and high gain

Complementary N- and P-channel devices

These enhancement-mode (normally-off) transistors utilize a

vertical DMOS structure and Supertex’s well-proven silicon-gate

manufacturing process. This combination produces devices with

the power handling capabilities of bipolar transistors and with the

high input impedance and positive temperature coefficient inher-

ent in MOS devices. Characteristic of all MOS structures, these

devices are free from thermal runaway and thermally-induced

secondary breakdown.

Supertex’s vertical DMOS FETs are ideally suited to a wide range

of switching and amplifying applications where high breakdown

voltage, high input impedance, low input capacitance, and fast

switching speeds are desired.

Applications

Motor controls

Converters

Amplifiers

Switches

Power supply circuits

Drivers (relays, hammers, solenoids, lamps,

memories, displays, bipolar transistors, etc.)

Package Options

Absolute Maximum Ratings

Drain-to-Source VoltageBV

Drain-to-Gate VoltageBV

Gate-to-Source Voltage± 30V

Operating and Storage Temperature-55°C to +150°C

Soldering Temperature*300°C

*

Distance of 1.6 mm from case for 10 seconds.

Note: See Package Outline section for dimensions.

DSS

DGS

S G D

TO-92

7-15

2N7008

Thermal Characteristics

PackageI (continuous)*I (pulsed)Power DissipationI*I

TO-92230mA1.3A1W125170230mA1.3A

DDjcjaDRDRM

@ T = 25CC/WC/W

C

°°°

θθ

*

I (continuous) is limited by max rated T.

Dj

Electrical Characteristics

(@ 25°C unless otherwise specified)

SymbolParameterMinTypMaxUnitConditions

BV Drain-to-Source Breakdown Voltage60VI = -10µA, V = 0V

DSSDGS

VGate Threshold Voltage12.5VV = V, I = 250µA

GS(th)GSDSD

IGate Body Leakage100nAV = ±30V, V = 0V

GSSGSDS

IZero Gate Voltage Drain Current1µAV = 0V, V = 50V

DSSGSDS

500µAV = 0V, V = 50V

ION-State Drain Current500mAV = 10V, V ≥ 2V

D(ON)GSDSDS(ON)

R Static Drain-to-Source ON-State Resistance7.5V = 5V, I = 50mA

DS(ON)GSD

GForward Transconductance80mV = 10V, I = 0.2A

FSDSD

CInput Capacitance50

ISS

CCommon Source Output Capacitance25pF

OSS

CReverse Transfer Capacitance5

RSS

tTurn-ON Time20

(ON)

tTurn-OFF Time20

(OFF)

VDiode Forward Voltage Drop1.5VI = 150mA, V = 0V

SDSDGS

ns

V = 0V, V = 25V

GSDS

f = 1 MHz

V = 30V, I =200 mA,

DDD

R = 25Ω

GEN

7.5V = 10V, I = 500mA

Ω

Ω

GSDS

T = 125°C

A

GSD

Notes:

1.All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)

2.All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

10V

INPUT

0V

10%

t

(ON)

t

d(ON)

V

DD

OUTPUT

0V

90%

90%

10%

t

r

t

(OFF)

t

d(OFF)

t

F

10%

INPUT

90%

PULSE

GENERATOR

R

gen

V

DD

R

L

OUTPUT

D.U.T.

7-16

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enhancement