How to configure the RK3568 ETH0_REFCLKO_25M pin to operate at 25MHz? Currently, it outputs a frequency of 125MHz. This pin is used for clocking the KSZ9031 Ethernet PHY. Current settings dts:

 &gmac0 {
clock_in_out = "output";
phy-handle = <&rgmii_phy0>;
phy-mode = "rgmii";
phy-supply = <&vcc3v3_sys>;
pinctrl-names = "default";
pinctrl-0 =<&gmac0_miim 
            &gmac0_tx_bus2 
            &gmac0_rx_bus2 
            &gmac0_rgmii_clk 
            &gmac0_rgmii_bus
            &eth0_pins
            &eth0_reset>;
tx_delay = <0x10>;
rx_delay = <0x10>;
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 100000>;

status = "okay";};

&mdio0 {
rgmii_phy0: phy@2 {
    compatible = "ethernet-phy-ieee802.3-c22";
    reg = <0x2>;
    clocks = <&cru CLK_MAC0_REFOUT>;
    clock-frequency = <25000000>;
    
};};

The name corresponds to the pin on the board. Initially, I found a DTS example for the RK3588. In the documentation for both processors, there is a description of the functionality showing that they can act as a clock generator for the PHY—in this case, 25 MHz. The RK3588 has an example configuration: In rockchip,rk3588-cru.h, there is a specific identifier for the ETH0_REFCLKO_25M clock—its name is REFCLKO25M_ETH0_OUT. I couldn't find a similar identifier in rk3568-cru.h.

Definitions from the DTSI for CRU:

    cru: clock-controller@fdd20000 {
    compatible = "rockchip,rk3568-cru";
    reg = <0x0 0xfdd20000 0x0 0x1000>;
    clocks = <&xin24m>;
    clock-names = "xin24m";
    #clock-cells = <1>;
    #reset-cells = <1>;
    assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
    assigned-clock-rates = <32768>, <1200000000>, <200000000>;
    assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
    rockchip,grf = <&grf>;
};

Definitions from the DTSI for GMAC0:

    gmac1: ethernet@fe010000 {
    compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
    reg = <0x0 0xfe010000 0x0 0x10000>;
    interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
             <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
    interrupt-names = "macirq", "eth_wake_irq";
    clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
         <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
         <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
         <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
    clock-names = "stmmaceth", "mac_clk_rx",
              "mac_clk_tx", "clk_mac_refout",
              "aclk_mac", "pclk_mac",
              "clk_mac_speed", "ptp_ref";
    resets = <&cru SRST_A_GMAC1>;
    reset-names = "stmmaceth";
    rockchip,grf = <&grf>;
    snps,axi-config = <&gmac1_stmmac_axi_setup>;
    snps,mixed-burst;
    snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
    snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
    snps,tso;
    status = "disabled";

    mdio1: mdio {
        compatible = "snps,dwmac-mdio";
        #address-cells = <0x1>;
        #size-cells = <0x0>;
    };

    gmac1_stmmac_axi_setup: stmmac-axi-config {
        snps,blen = <0 0 0 0 16 8 4>;
        snps,rd_osr_lmt = <8>;
        snps,wr_osr_lmt = <4>;
    };

    gmac1_mtl_rx_setup: rx-queues-config {
        snps,rx-queues-to-use = <1>;
        queue0 {};
    };

    gmac1_mtl_tx_setup: tx-queues-config {
        snps,tx-queues-to-use = <1>;
        queue0 {};
    };
};

At this stage, I am configuring Barebox (version v2025.02.0). Using CLK_MAC0_REFOUT is just my assumption — I couldn't find any confirmation in the TRM or Datasheet. Maybe there's a better source for this?