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x86 - In a hyper-threading scenario, does one logical core entering protected mode (ring 0) affect the instructions on another l

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When the workload on the CPU enters kernel mode, the CPU itself also enters protected mode (Ring 0) accordingly.

On a machine with hyper-threading enabled, is the control scope of protected mode at the logical core level or the physical core level?

  • If the entire physical core synchronously enters protected mode, will the behavior of a neighboring logical core running a user mode program be affected, such as being forced to pause or wait?
  • If it is not affected, how does the CPU differentiate between instructions from different logical cores and grant them different permissions? How does protected mode work?

When the workload on the CPU enters kernel mode, the CPU itself also enters protected mode (Ring 0) accordingly.

On a machine with hyper-threading enabled, is the control scope of protected mode at the logical core level or the physical core level?

  • If the entire physical core synchronously enters protected mode, will the behavior of a neighboring logical core running a user mode program be affected, such as being forced to pause or wait?
  • If it is not affected, how does the CPU differentiate between instructions from different logical cores and grant them different permissions? How does protected mode work?
Share Improve this question asked Jan 20 at 4:40 Frontier_SetterFrontier_Setter 6494 silver badges15 bronze badges
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It has to be per logical core; the alternative would be unusable. Logical cores are supposed to be able to run different threads or processes that run independently, including being able to make system calls and enter/exit the kernel independently of each other.

It's easy to achieve by giving each logical core its own copy of the relevant control and descriptor table registers, which are what is checked to determine whether the instruction succeeds or generates a protection fault. Then different logical cores can be in different modes simply by having different values in those registers.

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